1. Technical Field
Each of FIGS. 1 and 9A and 9B of Patent Literature 1 describes a memory module including buffers, for example. Provision of the buffer between each memory on the memory module and a controller not shown in Patent Literature 1 allows signal quality between the memory and the controller to be maintained at a high level.
JP Patent Kohyou Publication No. JP2010-524089A, which corresponds to US2008/080261A1, U.S. Pat. No. 7,562,271B2, US2011/228614A1, US2010/146199A1, U.S. Pat. No. 8,108,607B2, US2009/198924A1 and U.S. Pat. No. 7,685,364B2
2. Discussion of Related Art
The entire disclosures of the above mentioned Patent Literature are incorporated herein by reference thereto. The following analyses are given by the present invention.
As indicated in Patent Literature 1, it is extremely important to enhance the signal quality between the memory chip and the controller in the system, in terms of system design. Specifically, due to lower-voltage/higher-speed operation in recent years, the size of a so-called data eye decreases. Accordingly, a system with a higher signal quality is demanded.
It is one idea to perform buffering between the controller and the memory chip in order to enhance the signal quality, as described in Patent Literature 1. However, as will be described below in detail, it is desirable to also cope with signal quality degradation caused by a stub created when wiring is branched.
A configuration and operation of a system using a DIMM (Dual Inline Memory Module) studied by the inventor of the present invention will be described with reference to FIG. 9. FIG. 9 shows a system using two memory modules D10 and D20.
Referring to FIG. 9, a plurality of memory chips are mounted on both sides of a module substrate of each of the memory modules D10 and D20. Memory chips M10 to M17 are mounted on one side of the module substrate of the memory module D10, and memory chips M20 to M27 are mounted on the other surface of the module substrate of the memory module D10. Similarly, memory chips M30 to M37 are mounted on one side of the module substrate of the memory module D20, and memory chips M40 to M47 are mounted on the other surface of the module substrate of the memory module D20. Buses of the controller CNT10 (which are 64 buses) are connected in common to the two memory modules D10 and D20.
The memory module D10 and the memory module D20 selectively operate due to activation of a chip select signal CS0 (shown in the diagram in the left side of FIG. 9) and a chip select signal CS1 (shown in the diagram in the right side of FIG. 9), respectively. When the chip select signal CS0 is activated, 16 memory chips M10 to M17 and M20 to M27 indicated in gray color (and mounted on both sides of the memory module D10) are activated. Assume that there are 4 DQ terminals per chip, in this case. Then, data at 64 data terminals are all accessed. On this occasion, the memory module D20 which operates according to activation of the chip select signal CS1 does not operate.
In the configuration shown in FIG. 9, data buses of the memory chips M30 to M37 and the memory chips M40 to M47 mounted on the memory module 20 which operates according to activation of the chip select signal CS1 are branched/connected, through the memory chips M30 to M37 and M40 to M47 are not accessed. Accordingly, there are long stubs. Signal reflection may thereby occur, leading to signal quality degradation.
Then, by providing buffers on each of the memory modules D10 and D20 as described in Patent Literature 1, signal quality can be improved more than in the configuration shown in FIG. 9. However, even if the buffers are provided, there is still a problem that signal quality degradation caused by a stub cannot be solved.